The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.
However, problems may arise as semiconductor technologies are continually progressing to smaller feature sizes, wherein “feature size” is a smallest size of a semiconductor feature that can be created by a particular photolithographic technology—meaning the smallest feature that can be etched onto the surface of a substrate by a fab facility's equipment—and still have the semiconductor feature function properly. For example, a feature could be a wire, a gate, or some other circuit component. When feature sizes shrink, the spacing between the features—or the pitch—shrinks as well. If the pitch gets small enough, a photolithography technology may have difficulties in forming a well defined pitch. Accordingly, a method to reduce the pitch without changing the photolithography technology is desired.